`timescale 1ns / 1ps
`define CLK_PERIOD 20
module iic_master_tb();

    reg                                           clk                       =0;
    always#(`CLK_PERIOD/2) clk = ~clk;
    wire                                 o_i2c_scl               ;
    wire                                 io_i2c_sda              ;
iic_test_top iic_test_top(
    .i_clk                                     (clk                    ),
    .o_i2c_scl                                 (o_i2c_scl              ),
    .io_i2c_sda                                (io_i2c_sda             ),
    .o_cep_en                                  (                       ) 
);

    defparam iic_test_top.iic_test.P_DELAY_CNT = 50_000;
eeprom eeprom(
    .scl                                       (o_i2c_scl              ),
    .sda                                       (io_i2c_sda             ) 
); 
endmodule
